1. Field of Invention
The present invention relates to a memory module controlling system. More particularly, the present invention relates to a system for controlling a high-speed memory module.
2. Description of Related Art
Memory is one of the most important components in a computer system. At present, dynamic random access memories (DRAMs) are one of the most commonly used memory chip. The development of DRAM is extremely fast these days. Memory capacity has increased from the former 1K bits per chip to more than 64M bits now. Although storage capacity has increased many folds, operating efficiency of DRAM has not improved that much. Compared with a processing device such as a microprocessor, the operating efficiency of DRAM is so poor that it can hardly match the speed of the microprocessor. Consequently, a number of complicated and expensive controlling systems are developed, mainly to increase the operating efficiency of memories. For example, synchronous random access memory caches (SRAM caches) and parallel arrays of DRAMs are recently developed memory controlling systems.
To resolve the problems of having a low operating efficiency and a complicated controlling scheme, Rambus corporation has developed a memory controlling system having a chip-to-chip bus interface, and has defined the protocols for its modular connection. This type of memory controlling system that follows a pre-defined set of rules for communication is generally referred to as having a direct Rambus channel configuration. Memories can be directly connected to a microprocessor, graphic processor or ASICs through a direct Rambus channel. The Rambus channel requires only a few high frequency carrier lines for carrying all the necessary information such as memory address, digital data and control signals. Memory module that uses the direct Rambus channel design approach and the protocols of communication are known as a Rambus DRAM module or a RIMM for short.
FIGS. 1A, 1B and 1C are respectively a four-channel, a two-channel and a single channel direct Rambus channel type of memory and its control interfaces. Memory chips 10 are connected serially together through a direct Rambus channel 12, and finally attached to a control interface 16 of a memory controller 14. As shown in FIGS. 1A through 1C, all the memory chips 10 are divided between channel groups with the memory chips 10 in each group connected serially together via a single channel 12. Since each channel 12 has a minimum data transmission rate of about 1.6G bits, the data transmission rates for the memory modules in FIGS. 1A, 1B and 1C are 6.4G bits, 3.2G bits and 1.6G bits, respectively. Hence, RIMM memory module is able to have a high operating efficiency but a low cost of production.
Although RIMM memory modules can operate at a very high speed, a high operating frequency of up to 400 MHz must be supplied. Hence, a terminal must be installed at the terminal of a channel for preventing reflection of high frequency signals.
FIG. 2A is a sketch showing a RIMM having three RIMM memory modules 20a, 20b and 20c plugged into their respective memory slots. Through a single channel 24, all the memory chips 22a, 22b and 22c in all three modules are connected serially together. The module 20a is connected to the control interface 26a of the memory controller 26 via the channel 24. The last module 20c is connected to a terminal 28 and a clock pulse generator 29 via the same channel 24. Therefore, the memory controller 26, the memory modules 20a, 20b, 20c and the terminal 28 together form a complete signaling circuit. However, if only a single RIMM memory module is plugged into any one of the memory slots, a complete circuit between the memory controller 26, the single memory module and the terminal 28 cannot be established. Under this circumstance, normal practice is to plug dummy RIMM modules such as 20b' and 20c' into the empty slots, as shown in FIG. 2B. Each of these dummy RIMM modules do not have memory chips like a RIMM memory module, instead each dummy module only contains a circuit channel for passing signals. Hence, a complete circuit linking the memory controller 26, the memory module 20a, the terminal 28 and the clock pulse generator 29 is now established, and information regarding memory address, data and control signals can be transmitted.
Therefore, the solution to signal cutoff when some slots contain no RIMM memory is to plug in dummy modules having a channel circuit therein as a substitute. By so doing, all the memory slots are occupied. The dummy modules must be unplugged whenever additional RIMM memory modules need to be installed. In addition, the fabrication of dummy modules adds to the cost of production.
In light of the foregoing, there is a need to provide an easier method of connecting RIMM memory modules that can save cost.